The present invention relates to a data prefetch apparatus and, more particularly, to a data prefetch apparatus used for transferring data from a main memory to a peripheral unit.
In a data processing apparatus, a channel is generally arranged to perform data transfer between a main memory and a peripheral unit such as an input/output device (to be referred to as an I/O device hereinafter), independently of a central processing unit (to be referred to as a CPU hereinafter). A data buffer is arranged in the channel to perform high-speed data transfer. The data buffer stores memory data such as read data which is read out from the main memory to be transferred to the I/O device and write data which is transferred from the I/O device to be written in the main memory. Further, an address counter is arranged in the channel to generate a memory address in the main memory. For data transfer, a start address of a data transfer area of the main memory is set in the address counter. Every time the channel accesses the main memory to read out data therefrom, the address counter is incremented. A byte counter is arranged in an I/O controller to indicate the number of bytes of data to be transferred to the I/O device. Every time 1-byte data is transferred between the I/O device and the data buffer of the channel, the count of the byte counter is decremented. The I/O controller detects the count "0" of the byte counter and determines the termination of data transfer between the I/O device and data buffer.
For transferring data from the main memory to the I/O device, the channel generally prefetches data from the main memory if data transfer from the main memory to the I/O device is not completed and if data stored in the data memory is not full. It is known that the data transfer speed between the channel and the main memory is higher than that between the channel and the I/O device. By the time when all the transfer data from the main memory are supplied to the channel by memory data prefetch, data transfer from the data buffer of the channel to the I/O device is not completed. At this time, the count of the byte counter of the I/O controller is not "0". For this reason, the channel causes the address counter to increment until data transfer from the main memory to the I/O device is completed. Therefore, the channel prefetches data from a memory area exceeding the data transfer area of the main memory. As a result, when data transfer from the channel to the I/O device is completed, the count of the address counter may indicate a memory address which exceeds an end memory address (maximum possible address) of the main memory. In this case, a memory access error (over address error) occurs for the main memory. For designing a multiprocessing system having a common memory or a multiprocessing system which can access a memory of the other system, the over address error entails the following problem. Since the count of the memory address of the channel indicates the over address of the main memory, data in the memory of the other system or the common memory is erroneously read out. Therefore, if the over address access is left without any specific measure, trouble occurs when the memory of the other system is not connected to the multiprocessing system.
In order to solve the above problem, an end address register which stores the end address data and a comparator may be arranged in the channel. A memory address (B) indicated by the address counter is compared with the end memory address (A) stored in the end address register, by the comparator. A memory request is produced only if the memory address (B) is smaller than the end memory address (A). However, with this arrangement, an end address register and comparator which have a large capacity of bits are required, resulting in a complex system configuration. Further, the end memory address data must be preset in the end address register by programming. If the memory capacity of the main memory is changed, a new end memory address must be set in the end address register, thus requiring a cumbersome operation.